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up to 600 v to load v cc v b v s ho lo com hin v ss lin v cc v ss lin hin v cc v b v s ho lo com hin lin up to 600 v to load v cc lin hin typical connection high and low side driver features? floating channel designed for bootstrap operation ? fully operational to +600 v ? tolerant to negative transient voltage, dv/dt immun e ? gate drive supply range from 10 v to 20 v ? undervoltage lockout for both channels ? 3.3 v, 5 v, and 15 v input logic compatible ? matched propagation delay for both channels ? logic and power ground +/- 5 v offset ? l ower di/dt gate driver for better noise immunity ? outputs in phase with inputs (irs2106) packages irs2106/irs21064(s)pbf www.irf.com 1 data sheet no. pd60246 (refer to lead assignments for correct pinconfiguration). these diagrams show electri- cal connections only. please refer to our application notes and designtips for proper circuit board layout. description the irs2106/irs21064 are high voltage, high speed power mosfet and igbt drivers with independent high - an d low-side refe renced output channels. proprietary hvic and latch immune cmos technologies enable ruggedized monolithic con- struction. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. irs2106 irs21064 the output drivers feature a high pulse current buf fer stage designed for minimum driver cross-conduct ion. the floating channel can be used to drive an n-chan nel power mosfet or igbt in the high side configura tion which operates up to 600 v. part input logic cross- conduction prevention logic deadtime (ns) ground pins t o n /t o ff (ns) 2106/2301 com 21064 hin/lin no none v ss /com 220/200 2108 internal 540 com 21084 hin/lin yes programmable 540 - 5000 v ss /com 220/200 2109/2302 internal 540 com 21094 in/sd yes programmable 540 - 5000 v ss /com 750/200 feature comparison 2304 hin/lin yes internal 100 com 160/140 14-lead pdip 14-lead soic 14-lead pdip 8-lead pdip 8-lead soic ? rohs compliant downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 2 symbol definition min. max. units v b high-side floating absolute voltage -0.3 625 v s high-side floating supply offset voltage v b - 25 v b + 0.3 v ho high-side floating output voltage v s - 0.3 v b + 0.3 v cc l ow-side and logic fixed supply voltage -0.3 2 5 v lo l ow-side output voltage -0.3 v cc + 0.3 v in logic input voltage v ss - 0.3 v cc + 0.3 v ss logic ground (irs21064 only) v cc - 25 v cc + 0.3 dv s /dt allowable offset supply voltage transient 50 v/ns (8 lead pdip) 1.0 p d package power dissipation @ t a +25 c (8 lead soi c) 0.625 (14 lead pdip) 1.6 (14 l ead soic) 1.0 (8 lead pdip) 125 rth ja thermal resistance, junction to ambient (8 lead soic) 200 (14 lead pdip) 75 (14 lead soic) 120 t j junction temperature 150 t s storage temperature -50 150 t l lead temperature (soldering, 10 seconds) 300 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all vo ltage param- eters are absolute voltages referenced to com. the thermal resistance and power dissipation ratings ar e measured under board mounted and still air conditions. v c c/w w downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 3 dynamic electrical characteristics v bias (v cc , v bs ) = 15 v, v ss = com, c l = 1000 pf, t a = 25 c. symbol definition min. typ. max. units test conditions t on turn-on propagation delay 220 300 v s = 0 v t off turn-off propagation delay 200 280 v s = 0 v or 600 v mt delay matching, hs & ls turn-on/off 0 30 t r turn-on rise time 10 0 22 0 t f turn-off fall time 3 5 8 0 ns note 1: l ogic operational for v s of -5 v to +600 v. logic state held for v s of -5 v to -v bs . (please refer to the design tip dt97-3 for more details). v b high-side floating supply absolute voltage v s + 10 v s + 20 v s high-side floating supply offset voltage note 1 60 0 v ho high-side floating output voltage v s v b v cc l ow-side and logic fixed supply voltage 1 0 2 0 v lo l ow-side output voltage 0 v cc v in l ogic input voltage v ss v cc v ss logic ground (irs21064 only) -5 5 t a ambient temperature -40 125 c v symbol definition min. max. units recommended operating conditions the input/output logic timing diagram is shown in f ig. 1. for proper operation the device should be us ed within the recommended conditions. the v s and v ss offset rating are tested with all supplies biased at a 15 v differential. v s = 0 v downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 4 static electrical characteristics v bias (v cc , v bs ) = 15 v, v ss = com and t a = 25 c unless otherwise specified. the v il , v ih, and i in parameters are referenced to v ss /com and are applicable to the respective input leads. the v o , i o, and r on parameters are referenced to com and are applicable to the respective output leads: ho and lo. symbol definition min. typ. max. units test conditions v ih logic 1 input voltage 2.5 v il logic 0 input voltage 0.8 v oh high level output voltage, v bias - v o 0.05 0.2 v ol low level output voltage, v o 0.02 0.1 i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 20 75 130 i qcc quiescent v cc supply current 60 120 180 i in+ logic 1 input bias current v in = 5 v 5 20 i i n - l ogic 0 input bias current v in = 0 v 5 v ccuv+ v cc and v bs supply undervoltage positive going 8.0 8.9 9.8 v bsuv+ threshold v ccuv- v cc and v bs supply undervoltage negative going 7.4 8.2 9.0 v bsuv- threshold v ccuvh hysteresis 0.3 0.7 v bsuvh i o+ output high short circuit pulsed current 130 290 v o = 0 v, pw 10 s i o- output low short circuit pulsed current 270 600 v o = 15 v, pw 10 s v a v v cc = 10 v to 20 v i o = 2 ma v in = 0 v or 5 v ma downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 5 functional block diagrams irs2106 lin uv detect delay com lo vcc hin vs ho vb pulse filter hv level shifter rr s q uv detect pulse generator vss/com level shift vss/com level shift irs21064 lin uv detect delay com lo vcc hin vss vs ho vb pulse filter hv level shifter rr s q uv detect pulse generator vss/com level shift vss/com level shift downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 6 14 lead pdip 14 lead soic irs21064pbf irs21064spbf lead assignments 8 lead pdip 8 lead soic lead definitions symbol description hin l ogic input for high-side gate driver output (ho), in phase lin l ogic input for low-side gate driver output (lo), in phase vss logic ground (irs21064 only) v b high-side floating supply h o high-side gate drive output v s high-side floating supply return v cc l ow-side and logic fixed supply lo l ow-side gate drive output co m l ow-side return irs2106pbf irs2106spbf 1 2 3 4 8 7 6 5 v cc hin lin com v b ho v s lo 1 2 3 4 8 7 6 5 v cc hin lin com v b ho v s lo 1 2 3 4 5 6 7 1 4 13 12 11 10 9 8 v cc hin lin vss com lo v b ho v s 1 2 3 4 5 6 7 1 4 13 12 11 10 9 8 v cc hin lin vss com lo v b ho v s downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 7 figure 3. delay matching waveform definitions hin lin ho 50% 50% 10% lo 90% mt ho lo mt figure 1. input/output timing diagram hin lin ho lo figure 2. switching time waveform definitions hin lin t r t on t f t off ho lo 50% 50% 90% 90% 10% 10% downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 8 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 t e m pe r a t u r e ( o c) t u r n - o n p r o p ag a t i on d e l ay ( n s ) typ. max 0 100 200 300 400 500 10 12 14 16 18 20 v b i as supply voltage (v) t u r n - o n p r o p a ga t i o n d e l a y ( n s ) typ. max. 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 t e m pe r a t u r e ( o c) t u r n - o f f p r opa g a t i o n d e l ay ( n s ) max. typ. 0 100 200 300 400 500 10 12 14 16 18 20 v b i as s u p p l y v o l t age ( v ) t u r n - o f f p r opa g a t i o n d e l ay ( n s ) typ. max. figure 4a. turn-on propagation delay vs. temperature figure 4b. turn-on propagation delay vs. supply voltage figure 5a. turn-off propagation delay vs. temperature figure 5b. turn-off propagation delay vs. supply volta ge downloaded from: http:///
i r s 2 1 0 6 / i r s 2 1 0 6 4 ( s ) p bf ww w .irf . c om 9 fig u r e 6 a . t u r n - o n r i se ti me v s . t e m p e r a t u re f i gu r e 6 b . t u r n - o n r i s e t i me v s . s uppl y v o l t a ge f i g u r e 7 a . tu r n - o f f f a l l t i me v s . t e m p e r a t u re f i g u r e 7 b . tu r n - o f f f a l l t i me vs . s u p p l y v o l ta ge 0 1 00 2 00 3 00 4 00 5 00 - 50 - 25 0 25 50 75 1 00 1 25 t e m p e r a t u r e ( o c ) 0 1 00 2 00 3 00 4 00 5 00 10 12 14 16 18 20 v b ias supply voltage (v) m a x. m a x. t y p. t y p. 0 50 100 150 200 - 50 - 25 0 25 50 75 1 00 1 25 t e m p e r a t u r e ( o c) 0 50 1 00 1 50 2 00 10 12 14 16 18 20 i n pu t v o lt a g e ( v) t y p. m a x. t y p. m a x. turn-on rise time (ns) turn-on rise time (ns) turn-off rise time (ns) turn-off rise time (ns)
i r s 2 1 0 6 / i r s 2 1 0 6 4 ( s ) p bf ww w .irf . c om 10 0 .0 0 .8 1 .6 2 .4 3 .2 4 .0 - 50 - 25 0 25 50 75 100 125 t e m p e r a t u r e ( o c) i n p u t v o l t a g e ( v ) f i g u r e 9a . l o g i c " 0 " i n pu t v o l t a ge m i n. 0 .0 0 .8 1 .6 2 .4 3 .2 4 .0 10 12 14 16 18 20 v cc s u pp l y v o l t ag e ( v) i npu t v o l t a g e ( v) m i n. f i gu r e 8 a . l og i c 1 i np u t v o l t a ge v s . t e m p e r a t u re f i g u r e 8 b . l o g i c 1 i np u t v o l t a ge v s . s uppl y v o l t a ge f i gu r e 9 a . l og i c 0 i np u t v o l t a ge v s . t e m p e r a t u re f i g u r e 9 b . l o g i c 0 i np u t v o l t a ge vs . s u p p l y v o l ta ge 0 1 2 3 4 5 6 7 8 10 12 14 16 18 20 v bias s up p l y v o l t ag e ( v) i n p u t v o l t a g e ( v) 0 1 2 3 4 5 6 7 8 - 50 - 25 0 25 50 75 100 1 25 t e m p e r a t u r e ( o c) i p nput voltage (v) m i n. m in. max. max.
irs2106/irs21064(s)pbf www.irf.com 11 figure 10a. high level output voltage vs. temperature figure 10b. high level output voltage vs. supply voltage figure 11a. low level output voltage vs. temperature figure 11b. low level output voltage vs. supply volta ge 0.0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v bia s s upp l y v o l t age ( v ) h i gh l e v e l o u t p ut v o l t a g e ( v ) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 t e m pe r a t u r e ( o c) h i gh l e v e l o u t p ut v o l t a ge ( v ) 0.0 0.1 0.2 0.3 0.4 0.5 -50 -25 0 25 50 75 100 125 t e m pe r a t u r e ( o c) l ow l e v e l o u t p ut v o l t a g e ( v ) 0 0.1 0.2 0.3 0.4 0.5 10 12 14 16 18 20 v b i as s u p p ly v o l t a g e ( v ) l ow l e v e l o u t p ut v o l t a g e ( v ) max. typ. max. typ. max. typ. max. typ. high level output v ol t age (v) high level output v ol t age (v) low level output v ol t age (v) low level output v ol t age (v) downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 12 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 t e m p e r a t u r e ( o c) o f f s et s upp l y l ea k age c u r r e n t ( m a) max. 0 100 200 300 400 500 0 100 200 300 400 500 600 v b b oo s t v o l t a g e ( v ) o f f s et s up p l y lea k age c u r r e n t ( m a) max. 0 100 200 300 400 -50 -25 0 25 50 75 100 125 t e m p e r a t u r e ( o c) v bs s upp l y c u r r ent ( m a) typ. max. mi n. 0 100 200 300 400 10 12 14 16 18 20 v bs s u pp l y v o l t age ( v ) v bs s u pp l y c u r r ent ( m a) typ. max. mi n. figure 12a. offset suppl leakage current vs. temperature figure 12b. offset suppl leakage current vs. suppl voltage figure 13a. v bs suppl current vs. temperature figure 13b. v bs suppl current vs. suppl volta ge downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 13 0 100 200 300 400 10 12 14 16 18 20 v cc supply voltage (v) v cc s up p l y c u r r e n t ( m a) max. typ. mi n. 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 t e m p e r a t u r e ( o c) l o g i c " 1 " i n put c u r r e n t ( m a) typ. max. 0 10 20 30 40 50 60 10 12 14 16 18 20 v cc supply voltage (v ) l o g i c " 1 " i n put c u r r e n t ( m a) max. typ. figure 14a. quiescent v cc supply current vs. temperature figure 14b. quiescent v cc supply current vs. v cc supply voltage figure 15a. logic 1 input current vs. temperature figure 15b. logic 1 bias current vs. supply volta ge 0 100 200 300 400 -50 -25 0 25 50 75 100 125 temperature ( o c) vcc suppl y current ( m a ) m ax. typ. mi n. downloaded from: http:///
i r s 2 1 0 6 / i r s 2 1 0 6 4 ( s ) p bf ww w .irf . c om 14 7 8 9 10 11 12 - 50 - 25 0 25 50 75 1 00 1 25 t e m pe r a t u r e ( o c) v c c uv lo thr es hold ( +) ( v ) t y p. m a x. m i n. 6 7 8 9 10 11 - 50 - 25 0 25 50 75 100 1 25 t e m pe r a t u r e ( o c) v c c uv lo thr es hold (- ) ( v ) t y p. m a x. m i n. fi g u r e 1 7 . v cc u nd e r v ol t a g e t h r es h old ( +) v s . t e m p e r a t u re figu r e 18 . v cc u nd e r v ol t a g e t h r es hold (-) v s . t e m p e r a t u re m ax 0 1 2 3 4 5 6 - 50 - 25 0 25 50 75 1 00 1 25 t e m p e r a t u r e ( c) logic "0" input bias current (a) figure 16a. logic "0" input bias current vs. temperature m ax 0 1 2 3 4 5 6 10 12 14 16 18 20 s u p p l y v o l t a g e ( v) logic "0" input bias current (a) figure 16b. logic "0" input bias current vs. voltage downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 15 7 8 9 10 11 12 -50 -25 0 25 50 75 100 125 t e m p e r a t u r e ( o c) v bs u v lo t h r e s ho l d ( + ) ( v ) typ. max. mi n. 6 7 8 9 10 11 -50 -25 0 25 50 75 100 125 t e m pe r a t u r e ( o c) v bs u v l o t h r e s h o l d ( - ) ( v ) typ. max. mi n. figure 19. v bs undervoltage threshold (+) vs. temperature figure 20. v bs undervoltage threshold (-) vs. temperature figure 21a. output source current vs. temperature figure 21b. output source current vs. supply volta ge 0 100 200 300 400 500 -50 -25 0 25 50 75 100 125 temperature ( o c) o utput source current (ma ) 0 100 200 300 400 500 10 12 14 16 18 20 v bias suppl y vol tage (v) output source current (ma ) max. typ. max. typ. downloaded from: http:///
irs2106/irs21064(s)pbf www.irf.com 16 -1 0 -8 -6 -4 -2 0 10 12 14 16 18 20 v bs f l o a t i n g s u p p l y v o l t a g e (v) v s offset supply voltage (v) t y p. figure 22a. output sink current vs. temperature figure 22b. output sink currentt vs. suppl voltag e figure 23. maximum v s negative offset vs. suppl voltage 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) t emprature ( o c) 70 v 140 v 0 v figure 24. irs2106 vs. frequenc (irfbc20), rgate=33 ? ? , vcc=15 v 0 200 400 600 800 1000 -50 -25 0 25 50 75 100 125 temperature ( o c) output sink current (ma) 0 200 400 600 800 1000 10 12 14 16 18 20 v bi as suppl y vol tage (v) output sink current (ma) max. tp. max. tp. downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 17 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 14 0 v 70 v 0 v figure 26. irs2106 vs. freque ncy (irfbc40), r gate =15 , v cc =15 v 20 40 60 80 10 0 1 2 0 14 0 1 10 100 1000 freq uency (khz) figure 25. irs2106 vs . fre quency (irfbc30), r gate =22 , v cc =15 v 1 40 v 0 v 70 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) figure 28. irs21064 vs. freque ncy (irfbc20), r gate =33 , v cc =15 v 1 4 0 v 0 v 7 0 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) figure 27. irs2106 vs. freque ncy (irfpe50), r gate =10 , v cc =15 v 0 v 14 0 v 7 0 v temperature ( o c ) downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 18 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 1 4 0 v 7 0 v 0 v figure 30. irs21064 vs. frequency (irfbc40), r gate =15 , v cc =15 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 1 4 0 v 7 0 v 0 v figure 29. irs21064 vs. frequency (irfbc30), r gate =22 , v cc =15 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 7 0 v 0 v figure 31. irs21064 vs. frequency (irfpe50), r gate =10 , v cc =15 v 1 40 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) figure 32. irs2106s vs. frequency (irfbc20), r gate =33 , v cc =15 v 0 v 7 0 v 1 4 0 v downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 19 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 0 v figure 34. irs2106s vs. frequency (irfbc40), r gate =15 , v cc =15 v 1 40 v 70 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 1 4 0 v 7 0 v 0 v figure 33. irs2106s vs. frequency (irfbc30), r gate =22 , v cc =15 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) tempreture ( o c) figure 35. irs2106s vs . fre que ncy (irfpe50), r gate =10 , v cc =15 v 1 40 v 70 v 0 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) 1 4 0 v 70 v 0 v figure 36. irs21064s vs. frequency (irfbc20), r gate =33 , v cc =15 v downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 20 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) figure 39. irs21064s vs . fre quency (irfpe50), r gate =10 , v cc =15 v 1 40 v 7 0v 0 v 20 40 60 80 10 0 12 0 14 0 1 10 100 1000 freq uency (khz) 1 4 0 v 7 0 v 0 v figure 37. irs21064s vs. freque ncy (irfbc30), r g ate = 2 2 , v c c = 1 5 v 20 40 60 80 100 120 140 1 10 100 1000 f r e q u e n c y ( k h z ) temperature ( o c) figure 38. irs21064s vs. frequency (irfbc40), r gate =15 , v cc =15 v temperature ( o c ) 14 0 v 70 v 0 v figure 38. irs21064s vs. frequency (irfbc40), r gate =15 , v cc =15 v downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 21 case outlines 01-6014 01-3003 01 (ms-001ab) 8 lead pdip 01-6027 01-0021 11 (ms-012aa) 8 lead soic 87 5 65 d b e a e 6x h 0.25 [ .010] a 6 4 3 12 4. outline conforms to jedec outline ms-012aa. notes: 1. dimensioning & tolerancing per asme y14.5m-1994 . 2. controlling dimension: millimeter 3. dimensions are shown in millimeters [inches]. 7 k x 45 8x l 8x c y footprint 8x 0.72 [.028] 6.46 [.255] 3x 1.27 [.050] 8x 1.78 [.070] 5 dimension does not include mold protrusions. 6 dimension does not include mold protrusions. mold protrusions not to exceed 0.25 [.010]. 7 dimension is the length of lead for soldering t o a substrate. mold protrusions not to exceed 0.15 [.006]. 0.25 [.010] cab e1 a a1 8x b c 0.10 [.004] e1 d e y b a a1 h k l .189 .1497 0 .013 .050 basic .0532 .0040 .2284 .0099 .016 .1968 .1574 8 .020 .0688 .0098 .2440 .0196 .050 4.80 3.80 0.33 1.35 0.10 5.80 0.25 0.40 0 1.27 basic 5.00 4.00 0.51 1.75 0.25 6.20 0.50 1.27 min max millimeters i n c h e s min max dim 8 e c .0075 .0098 0.19 0.25 .025 basic 0.635 basic downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 22 01-6010 01-3002 03 (ms-001ac) 14 lead pdip 01-6019 01-3063 00 (ms-012ab) 14 lead soic (narrow bod) downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 23 carrier tape dimension for 8soicn code min max min max a 7 .9 0 8.1 0 0. 31 1 0 .3 18 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5 .4 5 5.5 5 0. 21 4 0 .2 18 e 6 .3 0 6.5 0 0. 24 8 0 .2 55 f 5 .1 0 5.3 0 0. 20 0 0 .2 08 g 1 .5 0 n/a 0.059 n/a h 1 .5 0 1.6 0 0. 05 9 0 .0 62 m etr ic im p erial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0. 76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 m etr ic im p erial e f a c d g a b h n ot e : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 8-lead soic downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 24 carrier tape dimension for 14soicn code min max min max a 7 .9 0 8.1 0 0. 31 1 0 .3 18 b 3.90 4.10 0.153 0.161 c 15.70 16.30 0.618 0.641 d 7 .4 0 7.6 0 0. 29 1 0 .2 99 e 6 .4 0 6.6 0 0. 25 2 0 .2 60 f 9 .4 0 9.6 0 0. 37 0 0 .3 78 g 1 .5 0 n/a 0.059 n/a h 1 .5 0 1.6 0 0. 05 9 0 .0 62 m etr ic im p erial reel d im ension s for 14so ic n code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1 .9 5 2.4 5 0. 76 7 0 .0 96 e 98.00 102.00 3.858 4.015 f n/a 22.40 n/a 0.881 g 18.50 21.10 0.728 0.830 h 16.40 18.40 0.645 0.724 m etr ic im p erial e f a c d g a b h n ot e : co ntrolling d imension in mm load ed ta pe feed direction a h f e g d b c tape & reel 14-lead soic downloaded from: http:///
irs2106/irs21064(s)pbf .irf.com 25 order information 8-lead pdip irs2106pbf 14-lead pdip irs21064pbf 8-lead soic irs2106spbf 14-lead soic irs21064spbf 8-lead soic t ape & reel IRS2106STRPBF 14-lead soic t ape & reel irs21064strpbf ir world headquarters : 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 leadfree p art marking inform a tion lead free released non-lead freereleased part number date code irsxxxxx yww? ?xxxx pin 1identifier ir logo lot code (prod mode - 4 digit spn code) assembly site codeper scop 200-002 p ? marking code soic8 & 14 are msl 2 qualified. this product has been designed and qualified for the industrial level. qualification standards can be found at www.irf.com data and specifications subject to change without notice. 12/4/2006 downloaded from: http:///

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